MNSC140CORE datasheet(36/80 Pages) FREESCALE

36 / 80 page

MSC8102 Quad Core Digital Signal Processor, Rev. 12

2-6

Freescale Semiconductor

Specifications

2.5.3

Clock and Timing Signals

The following sections include a description of clock signal characteristics. Table 2-6 shows the maximum

frequency values for internal (core, reference, bus, and DSI) and external (CLKOUT) clocks. The user must ensure

that maximum frequency values are not exceeded.

Table 2-6.

Maximum Frequencies

Characteristic

Maximum in MHz

Core frequency

250/275

Reference frequency (REFCLK)

83.3/91.7

Internal bus frequency (BLCK)

83.3/91.7

DSI clock frequency (HCLKIN)

if REFCLK

≤ 70 MHz, HCLKIN ≤CLKOUT

if REFCLK > 70 MHz, HCLKIN

≤70 MHz

External clock output frequency (CLKOUT)

83.3/91.7

Note:

The REFCLK is CLKOUT.

Table 2-7.

Clock Frequencies

Characteristics

Symbol

250 MHz Device

275 MHz Device

Min

Max

Min

Max

CLKIN frequency

FCLKIN

33 MHz

75 MHz

33 MHz

75 MHz

DLLIN frequency

FDLLIN

33 MHz

75 MHz

33 MHz

75 MHz

BCLK frequency

FBCLK

33 MHz

75 MHz

33 MHz

75 MHz

Reference Clock (REFCLK) frequency

FREFCLK

33 MHz

83.3 MHz

33 MHz

91.7 MHz

Output Clock (CLKOUT) frequency

FCLKOUT

33 MHz

83.3 MHz

33 MHz

91.7 MHz

SC140 core clock frequency

FCORE

165 MHz

250 MHz

165 MHz

275 MHz

Note:

The rise and fall time of external clocks should be 5 ns maximum.

Table 2-8.

System Clock Parameters

Characteristic

Minimum

Maximum

Unit

Phase jitter between BCLK and DLLIN

—

0.5

CLKIN frequency

MHz

CLKIN slope

—

DLLIN slope

—

CLKOUT frequency jitter

—

(0.01

× FCLKOUT) + FCLKIN jitter

MHz

CLKOUT phase jitter (in DLLOFF mode)

—

Delay between CLKOUT and DLLIN

—

Notes:

Low CLKIN frequency causes poor PLL performance. Choose a FCLKIN value high enough to keep the frequency after

predivider (SPLLMFCLK) higher than 16.5 MHz.

Peak-to-peak.

Not tested. Guaranteed by design.

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