MPC8572ECLPXATLD datasheet(78/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 49 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Because LVDS clock driver’s common mode voltage is higher than the MPC8572E SerDes reference

clock input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the

LVDS output driver features 50-

Ω termination resistor. It also assumes that the LVDS transmitter

establishes its own common mode level without relying on the receiver or other external component.

Figure 49. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 50 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Because LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible

with MPC8572E SerDes reference clock input’s DC requirement, AC-coupling must be used. Figure 50

assumes that the LVPECL clock driver’s output impedance is 50

Ω. R1 is used to DC-bias the LVPECL

outputs prior to AC-coupling. Its value could be ranged from 140

Ω to 240Ω depending on clock driver

vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-

Ω termination

resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8572E SerDes

reference clock’s differential input amplitude requirement (between 200mV and 800mV differential peak).

For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock

input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25

Ω. Consult

n_REF_CLK

Clock Driver

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVDS CLK Driver Chip

10 nF

MPC8572E

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