MPC8572ECLPXATLD datasheet(55/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Local Bus Controller (eLBC)

Table 49 describes the general timing parameters of the local bus interface at BVDD = 2.5 V DC.

Output hold from local bus clock (except LAD/LDP and

LALE)

tLBKHOX1

0.7

—

Output hold from local bus clock for LAD/LDP

tLBKHOX2

0.7

—

Local bus clock to output high Impedance (except LAD/LDP

and LALE)

tLBKHOZ1

—2.5

Local bus clock to output high impedance for LAD/LDP

tLBKHOZ2

—2.5

Note:

1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,

tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock

reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the

tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.

3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock

for PLL bypass mode to 0.4

× BVDD of the signal in question for 3.3-V signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current

delivered through the component pin is less than or equal to the leakage current specification.

6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is

programmed with the LBCR[AHD] parameter.

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BVDD/2.

8. Guaranteed by design.

Table 49. Local Bus General Timing Parameters (BVDD = 2.5 V DC)—PLL Enabled

At recommended operating conditions with BVDD of 2.5 V ± 5%

Parameter

Symbol 1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

6.67

Local bus duty cycle

tLBKH/tLBK

—

LCLK[n] skew to LCLK[m] or LSYNC_OUT

tLBKSKEW

—

150

7, 8

Input setup to local bus clock (except LGTA/LUPWAIT)

tLBIVKH1

1.9

—

3, 4

LGTA/LUPWAIT input setup to local bus clock

tLBIVKH2

1.8

—

3, 4

Input hold from local bus clock (except

LGTA/LUPWAIT)

tLBIXKH1

1.1

—

3, 4

LGTA/LUPWAIT input hold from local bus clock

tLBIXKH2

1.1

—

3, 4

LALE output negation to high impedance for LAD/LDP

(LATCH hold time)

tLBOTOT

1.5

—

Local bus clock to output valid (except LAD/LDP and

LALE)

tLBKHOV1

—2.4

—

Table 48. Local Bus General Timing Parameters (BVDD = 3.3 V DC)—PLL Enabled (continued)

At recommended operating conditions with BVDD of 3.3 V ± 5%. (continued)

Parameter

Symbol 1

Min

Max

Unit

Notes

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