P89LPC9211FDH datasheet(41/75 Pages) NXP

41 / 75 page

P89LPC92X1

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Product data sheet

Rev. 2 — 1 December 2010

41 of 75

NXP Semiconductors

P89LPC9201/9211/922A1/9241/

8-bit microcontroller with 8-bit ADC

The overall connections to both comparators are shown in Figure 13. The comparators

function to VDD =2.4 V.

When each comparator is first enabled, the comparator output and interrupt flag are not

guaranteed to be stable for 10

μs. The corresponding comparator interrupt should not be

enabled during that time, and the comparator interrupt flag must be cleared before the

interrupt is enabled in order to prevent an immediate interrupt service.

When a comparator is disabled the comparator’s output, COn, goes HIGH. If the

comparator output was LOW and then is disabled, the resulting transition of the

comparator output from a LOW to HIGH state will set the comparator flag, CMFn. This will

cause an interrupt if the comparator interrupt is enabled. The user should therefore

disable the comparator interrupt prior to disabling the comparator. Additionally, the user

should clear the comparator flag, CMFn, after disabling the comparator.

7.24.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single

comparator input pin is used. The value of the internal reference voltage, referred to as

Vref(bg), is 1.23 V ± 10 %.

7.24.2 Comparator interrupt

Each comparator has an interrupt flag contained in its configuration register. This flag is

set whenever the comparator output changes state. The flag may be polled by software or

may be used to generate an interrupt. The two comparators use one common interrupt

vector. If both comparators enable interrupts, after entering the interrupt service routine,

the user needs to read the flags to determine which comparator caused the interrupt.

7.24.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is

activated, but both comparators are disabled automatically in Total Power-down mode.

Fig 13. Comparator input and output connections

comparator 1

CP1

CN1

(P0.4) CIN1A

(P0.3) CIN1B

(P0.5) CMPREF

Vref(bg)

OE1

CO1

CMF1

interrupt

002aae433

CMP1 (P0.6)

CMF2

comparator 2

OE2

CO2

CMP2 (P0.0)

CP2

CN2

(P0.2) CIN2A

(P0.1) CIN2B

change detect

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