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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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S9S08QD2CSC bảng dữ liệu(PDF) 82 Page - Freescale Semiconductor, Inc |
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S9S08QD2CSC bảng dữ liệu(HTML) 82 Page - Freescale Semiconductor, Inc |
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82 / 198 page  Chapter 7 Central Processor Unit (S08CPUV2) MC9S08QD4 Series MCU Data Sheet, Rev. 6 82 Freescale Semiconductor 7.5 HCS08 Instruction Set Summary Table 7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode variation of each instruction. Table 7-2. Instruction Set Summary (Sheet 1 of 9) Source Form Operation Object Code Cyc-by-Cyc Details Affect on CCR VH I N Z C ADC #opr8i ADC opr8a ADC opr16a ADC oprx16,X ADC oprx8,X ADC ,X ADC oprx16,SP ADC oprx8,SP Add with Carry A ← (A) + (M) + (C) IMM DIR EXT IX2 IX1 IX SP2 SP1 A9 B9 C9 D9 E9 F9 9E D9 9E E9 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp – ADD #opr8i ADD opr8a ADD opr16a ADD oprx16,X ADD oprx8,X ADD ,X ADD oprx16,SP ADD oprx8,SP Add without Carry A ← (A) + (M) IMM DIR EXT IX2 IX1 IX SP2 SP1 AB BB CB DB EB FB 9E DB 9E EB ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp – AIS #opr8i Add Immediate Value (Signed) to Stack Pointer SP ← (SP) + (M) IMM A7 ii 2 pp – – – – – – AIX #opr8i Add Immediate Value (Signed) to Index Register (H:X) H:X ← (H:X) + (M) IMM AF ii 2 pp – – – – – – AND #opr8i AND opr8a AND opr16a AND oprx16,X AND oprx8,X AND ,X AND oprx16,SP AND oprx8,SP Logical AND A ← (A) & (M) IMM DIR EXT IX2 IX1 IX SP2 SP1 A4 B4 C4 D4 E4 F4 9E D4 9E E4 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 – – – ASL opr8a ASLA ASLX ASL oprx8,X ASL ,X ASL oprx8,SP Arithmetic Shift Left (Same as LSL) DIR INH INH IX1 IX SP1 38 48 58 68 78 9E 68 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp –– ASR opr8a ASRA ASRX ASR oprx8,X ASR ,X ASR oprx8,SP Arithmetic Shift Right DIR INH INH IX1 IX SP1 37 47 57 67 77 9E 67 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp –– BCC rel Branch if Carry Bit Clear (if C = 0) REL 24 rr 3 ppp – – – – – – C b0 b7 0 b0 b7 C |
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