S9S08QD2CSC datasheet(62/198 Pages) FREESCALE

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Chapter 5 Resets, Interrupts, and General System Control

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

5.8.5

System Options Register 2 (SOPT2)

This high-page register contains bits to configure MCU-specific features on MC9S08QD4 series devices.

5.8.6

System Device Identification Register (SDIDH, SDIDL)

These high-page read-only registers are included so host development systems can identify the HCS08

derivative and revision number. This allows the development software to recognize where specific

memory blocks, registers, and control bits are located in a target MCU.

321

COPCLKS1

000

Reset:

000

= Unimplemented or Reserved

1 This bit can be written only one time after reset. Additional writes are ignored.

Figure 5-6. System Options Register 2 (SOPT2)

Table 5-7. SOPT2 Register Field Descriptions

Field

Description

COPCLKS

COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.

0 Internal 32 kHz clock is source to COP.

1 Bus clock is source to COP.

321

REV3

REV2

REV1

REV0

ID11

ID10

ID9

ID8

Reset:

000

= Unimplemented or Reserved

1 The revision number that is hard coded into these bits reflects the current silicon revision level.

Figure 5-7. System Device Identification Register — High (SDIDH)

Table 5-8. SDIDH Register Field Descriptions

Field

Description

7:4

REV[3:0]

Revision Number — The high-order 4 bits of address SDIDH are hard coded to reflect the current mask set

revision number (0–F).

3:0

ID[11:8]

Part Identification Number — Each derivative in the HCS08 family has a unique identification number. The

MC9S08QD4 series is hard coded to the value 0x011. See also ID bits in Table 5-9.

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