Data Sheet

19

Rev. 1.0, 2008-12-04

TLE7184F

Interface, VDH Switch and INH Digital Output

8

Interface, VDH Switch and INH Digital Output

8.1

PWM Interface (IFMA)

The TLE7184F has an integrated interface supporting the typical PWM interface between a remote master ECU

and the µC. The link to the external master ECU is a single wire communication based on the battery voltage and

running typ. with about 10 to 400 Hz. The information is encoded in the duty cycle of the signal.

This communication line requires a signal conditioning to connect to the on board µC.

The integrated circuit supports the incoming data path.

The outgoing data path is formed by external components

Figure 8

Structure PWM Interface

The integrated circuitry is described in Figure 8.

The main task of this interface is level shifting and protection of the µC.

The IFuC signal is following the IFMA signal, passing the duty cycle information from IFMA to the IFuC.

The µC port is used as input and is listening to the IFuC signal. The voltage at IFMA is monitored. If IFMA is low

the IFuC open drain output is switched on - forcing the IFuC signal to low.

If IFMA is high, the IFuC open drain output is deactivated and the IFuC signal is pulled to high by the internal pull-

up resistor.

The IFMA input is used as well for wake-up. See Chapter 9.1

8.2

VDHS Switch

The System IC has an integrated switch connecting the VDH pin to the VDHS pin. This allows to place an external

voltage divider for VDH voltage monitoring at the VDHS pin and to disconnect this voltage divider from VDH during

sleep mode to assure low current consumption. The VDHS switch is only deactivated when the VDD regulator is

switched off.

8.3

Digital Output INHD

The System IC provides a digital output INHD showing the logic state of INH (e.g. KL15) after complete wake-up

of the driver (approx. 1ms). The input levels of INH for the INHD output are defined separately from the levels for

wake up. Voltage levels for INH wake up function please see Chapter 9.4 section Wake-up and go-to-sleep. The

output stage consists of an integrated low side switch with a pull-up resistor to VDD.

T1 control

uC

Interface_uC

GND

GND

TLE 7184 F

KL 30

Pull up

interface

ECU

T3

T1

VDD

VCC

IFuC

IFMA

T2

Wake up

10k