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TLE7184F bảng dữ liệu(PDF) 16 Page - Infineon Technologies AG |
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TLE7184F bảng dữ liệu(HTML) 16 Page - Infineon Technologies AG |
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16 / 35 page ![]() TLE7184F Shunt Signal Conditioning Data Sheet 16 Rev. 1.0, 2008-12-04 6.1.8 Input bias current (ISN,ISP to GND) I IB -300 ––µA V CM=0V; VISO=open 6.1.9 High level output voltage of ISO V OH V VDD- 0.2 – V VDD V I OH=-3mA 6.1.10 Low level output voltage of ISO V OL -0.1 – 0.2 V I OH=3mA 6.1.11 Output short circuit current I SC 5 ––mA – 6.1.12 Differential input resistance2) R I 100 – – k Ω – 6.1.13 Common mode input capacitance2) C CM – – 10 pF 10kHz 6.1.14 Common mode rejection ratio at DC CMRR = 20*Log((Vout_diff/Vin_diff) * (Vin_CM/Vout_CM)) C MRR 80 100 – dB – 6.1.15 Common mode suppression3) with CMS = 20*Log(Vout_CM/Vin_CM) Freq =100kHz Freq = 1MHz Freq = 10MHz C MS – 62 43 33 –dB V IN=360mV* sin(2* π*freq*t); R s=500Ω; Rfb=7500Ω 6.1.16 Slew rate d V/dt – 10 – V/µs Gain>= 5; R L=1.0kΩ; CL=500pF 6.1.17 Large signal open loop voltage gain (DC) A OL 80 100 – dB – 6.1.18 Unity gain bandwidth G BW 10 20 – MHz R L=1kΩ; CL=100pF 6.1.19 Phase margin 2) F M – 50 – ° Gain>= 5; R L=1kΩ; CL=100pF 6.1.20 Gain margin 2) A M –12 – dB R L=1kΩ; CL=100pF 6.1.21 Bandwidth B WG 1.6 ––MHz Gain=15; R L=1kΩ; CL=500pF; R s=500Ω 6.1.22 Output settle time to 98% R fb/RS=15 R fb/RS=75 t set1 – – 1 4.6 1.8 8 µs R L=1kΩ; C L=500pF; 0.3< V ISO< 4.8V; R s=500Ω 1) A minimum capacitance of 100pF is needed at the output of the OpAmp (parasitic or real capacitor) 2) Not subject to production test; specified by design 3) Without considering any offsets such as input offset voltage, internal miss match and assuming no tolerance error in external resistors. Electrical Characteristics - Current sense signal conditioning (cont’d) V S = 6.0 to 33 V, Tj = -40 °C to +150 °C, gain = 5 to 75, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)1) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. |
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