R26 datasheet(68/487 Pages) RENESAS

68 / 487 page

R8C/26 Group, R8C/27 Group

6. Voltage Detection Circuit

Rev.2.10

Sep 26, 2008

Page 49 of 453

REJ09B0278-0210

6.4

Voltage Monitor 1 Reset (J, K Version)

Table 6.5 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Reset. Figure 6.15 shows an

Example of Voltage Monitor 1 Reset Operation (J, K Version). To use the voltage monitor 1 reset to exit stop mode,

set the VW1C1 bit in the VW1C register to 1 (digital filter disabled).

NOTE:

1. When the VW1C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1

instruction).

Figure 6.15

Example of Voltage Monitor 1 Reset Operation (J, K Version)

Table 6.5

Procedure for Setting Bits Associated with Voltage Monitor 1 Reset

Step

When Using Digital Filter

When Not Using Digital Filter

Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled)

Wait for td(E-A)

Select the sampling clock of the digital filter

by the VW1F0 to VW1F1 bits in the VW1C

Set the VW1C7 bit in the VW1C register to 1

4(1)

Set the VW1C1 bit in the VW1C register to 0

(digital filter enabled)

Set the VW1C1 bit in the VW1C register to 1

(digital filter disabled)

5(1)

Set the VW1C6 bit in the VW1C register to 1 (voltage monitor 1 reset mode)

Set the VW1C2 bit in the VW1C register to 0

Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on)

−

Wait for 4 cycles of the sampling clock of the

digital filter

− (No wait time required)

Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 reset enabled)

Vdet1

Internal reset signal

VCC

The above applies under the following conditions.

• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)

• VW1C0 bit in VW1C register = 1 (voltage monitor 1 reset enabled)

• VW1C6 bit in VW1C register = 1 (voltage monitor 1 reset mode)

When the internal reset signal is held “L”, the pins, CPU and SFR are reset.

The internal reset signal level changes from “L” to “H”, and a program is executed beginning with the address indicated by

the reset vector.

Refer to 4. Special Function Registers (SFRs) for the SFR status after reset.

fOCO-S

× 32

When the VW1C1 bit is set

to 0 (digital filter enabled)

Internal reset signal

When the VW1C1 bit is set

to 1 (digital filter disabled)

and the VW1C7 bit is set

to 1

fOCO-S

× 32

VW1C1 and VW1C7: Bits in VW1C register

Sampling clock of

digital filter

× 4 cycles

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