ST10F272Z2Q3 datasheet(20/189 Pages) STMICROELECTRONICS

20 / 189 page

Pin data

ST10F272Z2

20/189

XTAL1

138

XTAL1

Main oscillator amplifier circuit and/or external clock input.

XTAL2

137

XTAL2

Main oscillator amplifier circuit output.

To clock the device from an external source, drive XTAL1 while leaving XTAL2

unconnected. Minimum and maximum high / low and rise / fall times specified in

the AC Characteristics must be observed.

XTAL3

143

XTAL3

32 kHz oscillator amplifier circuit input

XTAL4

144

XTAL4

32 kHz oscillator amplifier circuit output

When 32 kHz oscillator amplifier is not used, to avoid spurious consumption,

XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32

in RTCCON register shall be set. 32 kHz oscillator can only be driven by an

external crystal, and not by a different clock source.

RSTIN

140

Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for

a specified duration while the oscillator is running resets the ST10F272Z2. An

internal pull-up resistor permits power-on reset using only a capacitor connected

to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON

sequence.

RSTOUT

141

Internal Reset Indication Output. This pin is driven to a low level during hardware,

software or watchdog timer reset. RSTOUT remains low until the EINIT (end of

initialization) instruction is executed.

NMI

142

Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU

to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when

the PWRDN (power down) instruction is executed, the NMI pin must be low in

order to force the ST10F272Z2 to go into power down mode. If NMI is high and

PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal

mode.

If not used, pin NMI should be pulled high externally.

VAREF

A/D converter reference voltage and analog supply

VAGND

A/D converter reference and analog ground

RPD

Timing pin for the return from interruptible power down mode and synchronous /

asynchronous reset selection.

VDD

17, 46,

72,82,93

, 109,

126, 136

Digital supply voltage = + 5 V during normal operation, idle and power down

modes.

It can be turned off when Stand-by RAM mode is selected.

VSS

18,45,

55,71,

83,94,

110,

127, 139

Digital ground

V18

1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF)

must be connected between this pin and nearest VSS pin.

Table 2.

Pin description (continued)

Symbol

Type

Function

ST10F272Z2Q3 bảng dữ liệu(PDF) 20 Page - STMicroelectronics

ST10F272Z2Q3 bảng dữ liệu(HTML) 20 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL