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PSD813F2 bảng dữ liệu(PDF) 46 Page - STMicroelectronics

tên linh kiện PSD813F2
Giải thích chi tiết về linh kiện  Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V
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PSD813F2 bảng dữ liệu(HTML) 46 Page - STMicroelectronics

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Page register
PSD8XXFX
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Doc ID 7833 Rev 7
13
Page register
The 8-bit Page register increases the addressing capability of the MCU by a factor of up to
256. The contents of the register can also be read by the MCU. The outputs of the Page
register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector
Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the CPLD for general logic. See Application Note
AN1154.
Figure 11 shows the Page register. The eight flip-flops in the register are connected to the
internal data bus D0-D7. The MCU can write to or read from the Page register. The Page
register can be accessed at address location CSIOP + E0h.
Figure 11.
Page register
RESET
D 0-D 7
R/W
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3
DPLD
AND
CPLD
INTERNAL
SELECTS
AND LOGIC
PLD
PGR4
PGR5
PGR6
PGR7
AI02871B



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