PSD813F2 datasheet(71/128 Pages) STMICROELECTRONICS

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PSD8XXFX

I/O ports

Doc ID 7833 Rev 7

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16.6

Address In mode

For MCUs that have more than 16 address signals, the higher addresses can be connected

to port A, B, C, and D. The address input can be latched in the input macrocell (IMC) by

Address Strobe (ALE/AS, PD0). Any input that is included in the DPLD equations for the

SRAM, or primary or secondary Flash memory is considered to be an address input.

16.7

Data port mode

Port A can be used as a data bus port for a MCU with a non-multiplexed address/data bus.

The Data port is connected to the data bus of the MCU. The general I/O functions are

disabled in port A if the port is configured as a Data port.

16.8

Peripheral I/O mode

Peripheral I/O mode can be used to interface with external peripherals. In this mode, all of

port A serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is

enabled by setting Bit 7 of the VM register to a ’1.’ Figure 26 shows how port A acts as a bi-

directional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for

PSEL0 and/or PSEL1 must be written in PSDabel. The buffer is tri-stated when PSEL0 or

PSEL1 is not active.

Figure 26.

Peripheral I/O mode

16.9

JTAG in-system programming (ISP)

Port C is JTAG compliant, and can be used for in-system programming (ISP). You can

multiplex JTAG operations with other functions on port C because in-system programming

(ISP) is not performed in normal operating mode. For more information on the JTAG port,

see Section 19: Programming in-circuit using the JTAG serial interface.

PSEL0

PSEL1

PSEL

VM REGISTER BIT 7

PA0 - PA7

D0-D7

DATA BUS

AI02886

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