PSD813F2 datasheet(75/128 Pages) STMICROELECTRONICS

75 / 128 page

PSD8XXFX

I/O ports

Doc ID 7833 Rev 7

75/128

16.19

Enable Out

The Enable Out register can be read by the MCU. It contains the output enable values for a

given port. A 1 indicates the driver is in output mode. A 0 indicates the driver is in tri-state

and the pin is in input mode.

16.20

Ports A and B – functionality and structure

Ports A and B have similar functionality and structure, as shown in Figure 27. The two ports

can be configured to perform one or more of the following functions:

●

MCU I/O mode

●

CPLD Output – macrocells McellAB7-McellAB0 can be connected to port A or port B.

McellBC7-McellBC0 can be connected to port B or port C.

●

CPLD input – Via the input macrocells (IMC).

●

Latched Address output – Provide latched address output as per Table 22.

●

Address In – Additional high address inputs using the input macrocells (IMC).

●

Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew

rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain mode.

●

Data port – port A to D7-D0 for 8 bit non-multiplexed bus

●

Multiplexed Address/Data port for certain types of MCU bus interfaces.

●

Peripheral mode – port A only

Figure 27.

Port A and port B structure

DATA OUT

REG.

ADDRESS

MACROCELL OUTPUTS

ENABLE PRODUCT TERM (.OE)

ALE

READ MUX

CPLD - INPUT

CONTROL REG.

DIR REG.

INPUT

MACROCELL

ENABLE OUT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT

A OR B PIN

DATA OUT

ADDRESS

A[ 7:0] OR A[15:8]

AI02887

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