360J datasheet(61/68 Pages) INTEL

61 / 68 page

Datasheet

Package Mechanical Specifications and Pin Information

STPCLK#

Input

STPCLK# (Stop Clock), when asserted, causes the processor to enter

a low power Stop-Grant state. The processor issues a Stop-Grant

Acknowledge transaction, and stops providing internal clock signals

to all processor core units except the FSB and APIC units. The

processor continues to snoop bus transactions and service interrupts

while in Stop-Grant state. When STPCLK# is deasserted, the

processor restarts its internal clock to all units and resumes

execution. The assertion of STPCLK# has no effect on the bus clock;

STPCLK# is an asynchronous input.

TCK

Input

TCK (Test Clock) provides the clock input for the processor test bus

(also known as the Test Access Port).

TDI

Input

TDI (Test Data In) transfers serial test data into the processor. TDI

provides the serial input needed for JTAG specification support.

TDO

Output

TDO (Test Data Out) transfers serial test data out of the processor.

TDO provides the serial output needed for JTAG specification

support.

TEST1,

TEST2

Input

TEST1 and TEST2 must have a stuffing option of separate pull down

resistors to VSS.

THERMDA

Other

Thermal Diode Anode.

THERMDC

Other

Thermal Diode Cathode.

THERMTRIP#

Output

The processor protects itself from catastrophic overheating by use of

an internal thermal sensor. This sensor is set well above the normal

operating temperature to ensure that there are no false trips. The

processor will stop all execution when the junction temperature

exceeds approximately 125°C. This is signalled to the system by the

THERMTRIP# (Thermal Trip) pin.

TMS

Input

TMS (Test Mode Select) is a JTAG specification support signal used by

debug tools.

TRDY#

Input

TRDY# (Target Ready) is asserted by the target to indicate that it is

ready to receive a write or implicit writeback data transfer. TRDY#

must connect the appropriate pins of both FSB agents.

TRST#

Input

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#

must be driven low during power on Reset.

VCC

Input

Processor core power supply.

VCCA[3:0]

Input

VCCA provides isolated power for the internal processor core PLL’s.

VCCP

Input

Processor I/O power supply.

VCCQ[1:0]

Input

Quiet power supply for on die COMP circuitry. These pins should be

connected to VCCP on the motherboard. However, these connections should

enable addition of decoupling on the

VCCQ lines if necessary.

Table 16.

Signal Description (Sheet 7 of 8)

Name

Type

Description

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