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360J bảng dữ liệu(PDF) 15 Page - Intel Corporation |
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360J bảng dữ liệu(HTML) 15 Page - Intel Corporation |
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15 / 68 page ![]() Datasheet 15 Electrical Specifications 3 Electrical Specifications 3.1 Power and Ground Pins For clean, on-chip power distribution, the Celeron M processor has a large number of V CC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Please refer to the platform design guides for more details. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins. 3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the Celeron M processor core frequency is a multiple of the BCLK[1:0] frequency. The Celeron M processor uses a differential clocking implementation. 3.2 Voltage Identification and Power Sequencing The Celeron M processor uses six voltage identification pins, VID[5:0], to support automatic selection of power supply voltages. The VID pins for Celeron M processor are CMOS outputs driven by the processor VID circuitry. Table 1 specifies the voltage level corresponding to the state of VID[5:0]. |
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