MB90F337 datasheet(36/48 Pages) FUJITSU

36 / 48 page

MB90335 Series

DS07-13735-6E

(4) UART0, UART1 I/O extended serial timing

(VCC

= 3.3 V ± 0.3 V, VSS = 0.0 V, TA = -40 °C to +85 °C)

Notes :

• Above rating is the case of CLK synchronous mode.

• CL is a load capacitance value on pins for testing.

• tCP is the machine cycle period (unit : ns) . Refer to “ (1) Clock input timing”.

Parameter

Symbol

Pin name

Conditions

Value

Unit

Min

Max

Serial clock cycle time

tSCYC

SCKx

Internal shift clock

Mode output pin is

= 80 pF + 1 TTL

8 tCP

⎯

SCK

↓ → SOT delay time

tSLOV

SCKx

SOTx

− 80

+ 80

Valid SIN

→ SCK ↑

tIVSH

SCKx

SINx

100

⎯

SCK

↑ → valid

SIN hold time

tSHIX

SCKx

SINx

⎯

Serial clock H pulse width

tSHSL

SCKx, SINx

External shift clock

Mode output pin is

= 80 pF + 1 TTL

4 tCP

⎯

Serial clock L pulse width

tSLSH

SCKx, SINx

4 tCP

⎯

SCK

↓ → SOT delay time

tSLOV

SCKx

SOTx

⎯

150

Valid SIN

→ SCK ↑

tIVSH

SCKx

SINx

⎯

SCK

↑ → valid

SIN hold time

tSHIX

SCKx

SINx

⎯

• Internal shift clock mode

• External shift clock mode

SCK

SOT

SIN

tSCYC

tSLOV

tIVSH

tSHIX

0.8 V

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

SCK

SOT

SIN

tSLSH

tSHSL

tSLOV

tIVSH

tSHIX

0.2 VCC

0.8 VCC

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

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