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SPMCK16Z4MPV16 bảng dữ liệu(PDF) 448 Page - Freescale Semiconductor, Inc |
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SPMCK16Z4MPV16 bảng dữ liệu(HTML) 448 Page - Freescale Semiconductor, Inc |
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448 / 500 page ![]() REGISTER SUMMARY M68HC16 Z SERIES D-74 USER’S MANUAL D.8.13 Timer Interrupt Flag Registers 1 and 2 These registers show condition flags that correspond to GPT events. If the corre- sponding interrupt enable bit in TMSK1/TMSK2 is set, an interrupt occurs. I4/O5F — Input Capture 4/Output Compare 5 Flag When I4/O5 in PACTL is zero, this flag is set each time TCNT matches the TOC5 val- ue in TI4/O5. When I4/O5 in PACTL is one, the flag is set each time a selected edge is detected at the I4/O5 pin. OCF[4:1] — Output Compare Flags An output compare flag is set each time TCNT matches the corresponding TOC reg- ister. OCF[4:1] correspond to OC[4:1]. ICF[3:1] — Input Capture Flags A flag is set each time a selected edge is detected at the corresponding input capture pin. ICF[3:1] correspond to IC[3:1]. TOF — Timer Overflow Flag This flag is set each time TCNT advances from a value of $FFFF to $0000. PAOVF — Pulse Accumulator Overflow Flag This flag is set each time the pulse accumulator counter advances from a value of $FF to $00. PAIF — Pulse Accumulator Flag In event counting mode, this flag is set when an active edge is detected on the PAI pin. In gated time accumulation mode, it is set at the end of the timed period. D.8.14 Compare Force Register/PWM Control Register C Setting a bit in CFORC causes a specific output on OC or PWM pins. PWMC sets PWM operating conditions. TFLG1/TFLG2 — Timer Interrupt Flag Registers 1–2 $YFF922 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I4/O5F OCF[4:1] ICF[3:1] TOF 0 PAOVF PAIF 0 0 0 0 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFORC — Compare Force Register/PWM Control Register $YFF924 15 11 10 9 8 7 6 4 3 2 1 0 FOC 0 FPWMA FPWMB PPROUT PPR SFA SFB F1A F1B RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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