SPMCK16Z4MPV16 datasheet(445/500 Pages) FREESCALE

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M68HC16 Z SERIES

USER’S MANUAL

D-71

PCLKS — PCLK Pin State (Read Only)

I4/O5 — Input Capture 4/Output Compare 5

0 = Output compare 5 enabled

1 = Input capture 4 enabled

PACLK[1:0] — Pulse Accumulator Clock Select (Gated Mode)

Table D-45 shows the PACLK[1:0] bit field effects.

PACNT — Pulse Accumulator Counter

Eight-bit read/write counter used for external event counting or gated time accumula-

tion.

D.8.8 Input Capture Registers 1–3

TIC[1:3] — Input Capture Registers 1–3

$YFF90E – $YFF912

The input capture registers are 16-bit read-only registers used to latch the value of

TCNT when a specified transition is detected on the corresponding input capture pin.

They are reset to $FFFF.

D.8.9 Output Compare Registers 1–4

TOC[1:4] — Output Compare Registers 1–4

$YFF914 – $YFF91A

The output compare registers are 16-bit read/write registers which can be used as out-

put waveform controls or as elapsed time indicators. For output compare functions,

they are written to a desired match value and compared against TCNT to control spec-

ified pin actions. They are reset to $FFFF.

Table D-44 PAMOD and PEDGE Effects

PAMOD

PEDGE

Effect

PAI falling edge increments counter

PAI rising edge increments counter

Zero on PAI inhibits counting

One on PAI inhibits counting

Table D-45 PACLK[1:0] Effects

PACLK[1:0]

Pulse Accumulator Clock Selected

System clock divided by 512

Same clock used to increment TCNT

TOF flag from TCNT

External clock, PCLK

Freescale Semiconductor, Inc.

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