AT91SAM7SE512 datasheet(46/47 Pages) ATMEL

46 / 47 page

6222ES–ATARM–15-Dec-09

AT91SAM7SE512/256/32 Preliminary

Revision History

Doc. Rev

Comments

Change

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Ref.

6222AS

First issue

Revised Memories with condensed mapping.

Added Package Outlines and 144-ball LFBGA pin and ordering information.

#2709

6222BS

Section 12. “Ordering Information” on page 45 ordering information code reference changed

#3699

6222CS

Section 6.1 ”JTAG Port Pins”, Section 6.3 ”Reset Pin”, Section 6.5 ”SDCK Pin”, removed statement: “not 5V

tolerant”

Section 7.6 ”SDRAM Controller”, Mobile SDRAM controller added to SDRAMC features

INL and DNL updated in Section 10.14 ”Analog-to-Digital Converter”

“Features” on page 2, Fully Static Operation; added, up to 55 MHz at 1.8V and 85°C worst case conditions

Section 7.1 ”ARM7TDMI Processor”, Runs at up to 55 MHz, providing 0.9 MIPS/MHz (core supplied with 1.8V)

Section 7.8 ”Peripheral DMA Controller” PDC priority list added

Section 7.5 ”Static Memory Controller”, Multiple device adaptability includes: compliant w/PSRAM in

synchronous operations.

#3826

#4005

#3924

#3833

review

6222DS

Figure 8-1 ”AT91SAM7SE Memory Mapping” Compact Flash not shown w/EBI Chip Select 5. Compact Flash is

shown with EBI Chip Select 2.

Section 8.1.2.1 ”Flash Overview”, updated AT91SAM7SE32 ...”reads as 8192 32-bit words.”

Section 6. ”/O Lines Considerations”, “JTAG Port Pins”, “Test Pin”, “Reset Pin”, “ERASE Pin” descriptions

updated

4804

4512

5062

6222ES

Section 10.11 ”Timer Counter”, .....the TC has two output compare and one input capture per channel.

4209

6222FS

Features:

“Mode for General Purpose Two-wire UART Serial Communication” added to “Debug Unit (DBGU)”.

Signal Description:

Table 3-1, “Signal Description List”, AD0-AD3 and AD4-AD7 comments reversed.

System Controller:

Figure 9-1 ”System Controller Block Diagram”, ‘periph_nreset’ changed into ‘power_on_reset’ for RTT.

5846

5271

5222

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