AT91SAM7SE512 datasheet(33/47 Pages) ATMEL

33 / 47 page

6222ES–ATARM–15-Dec-09

AT91SAM7SE512/256/32 Preliminary Summary

9.5

Debug Unit

• Comprises:

– One two-pin UART

– One Interface for the Debug Communication Channel (DCC) support

– One set of Chip ID Registers

– One Interface providing ICE Access Prevention

•Two-pin UART

– USART-compatible User Interface

– Programmable Baud Rate Generator

– Parity, Framing and Overrun Error

– Automatic Echo, Local Loopback and Remote Loopback Channel Modes

• Debug Communication Channel Support

– Offers visibility of COMMRX and COMMTX signals from the ARM Processor

• Chip ID Registers

– Identification of the device revision, sizes of the embedded memories, set of

peripherals

– Chip ID is 0x272A 0A40 (VERSION 0) for AT91SAM7SE512

– Chip ID is 0x272A 0940 (VERSION 0) for AT91SAM7SE256

– Chip ID is 0x2728 0340 (VERSION 0) for AT91SAM7SE32

9.6

Periodic Interval Timer

• 20-bit programmable counter plus 12-bit interval counter

9.7

Watchdog Timer

• 12-bit key-protected Programmable Counter running on prescaled SLCK

• Provides reset or interrupt signals to the system

• Counter may be stopped while the processor is in debug state or in idle mode

9.8

Real-time Timer

• 32-bit free-running counter with alarm running on prescaled SLCK

• Programmable 16-bit prescaler for SLCK accuracy compensation

9.9

PIO Controllers

• Three PIO Controllers. PIO A and B each control 32 I/O lines and PIO C controls 24 I/O lines.

• Fully programmable through set/clear registers

• Multiplexing of two peripheral functions per I/O line

• For each I/O line (whether assigned to a peripheral or used as general-purpose I/O)

– Input change interrupt

– Half a clock period glitch filter

– Multi-drive option enables driving in open drain

– Programmable pull-up on each I/O line

– Pin data status register, supplies visibility of the level on the pin at any time

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