UJA1076 datasheet(23/47 Pages) NXP

23 / 47 page

UJA1076_2

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Product data sheet

Rev. 02 — 27 May 2010

23 of 47

NXP Semiconductors

UJA1076

High-speed CAN core system basis chip

mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and

enter Standby mode. The status of the wake-up pins can be read via the wake-up level

status bits (WLS1 and WLS2) in the WD_and_Status register (Table 4).

Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts

is enabled (WIC1

≠ 00 or WIC2 ≠ 00).

The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting

bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are

sampled continuously). The sampling will be performed on the rising edge of WBIAS (see

Figure 11). The sampling time, 16 ms or 64 ms, is selected via the Wake Bias Control bit

(WBC) in the Mode_Control register.

Figure 12 shows typical circuit for implementing cyclic sampling of the wake-up inputs.

Fig 11. Wake-up pin sampling synchronized with WBIAS signal

Fig 12. Typical application for cyclic sampling of wake-up signals

Wake-up int

WAKEx pin

WBIAS pin

WBIASI

(internal)

enable bias

disable bias

wake level latched

015aaa078

UJA1076

WAKE1

WAKE2

BAT

WBIAS

015aaa122

47 k

PDTA144E

sample of

WAKEx

sample of

WAKEx

sample of

WAKEx

GND

biasing of

switches

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