UJA1076 datasheet(21/47 Pages) NXP

21 / 47 page

UJA1076_2

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Product data sheet

Rev. 02 — 27 May 2010

21 of 47

NXP Semiconductors

UJA1076

High-speed CAN core system basis chip

• the SBC is in Normal mode (MC = 10 or 11)

• the transceiver is enabled (bit STBCC = 0; see Table 6)

and

• V2 is enabled and its output voltage is above its undervoltage threshold, Vuvd

• V2 is disabled but an external voltage source, or V1, connected to pin V2 is above its

undervoltage threshold (see Section 6.6.3)

In CAN Active mode, the transceiver can transmit and receive data via the CANH and

CANL pins. The differential receiver converts the analog data on the bus lines into digital

data which is output on pin RXDC. The transmitter converts digital data generated by a

CAN controller, and input on pin TXDC, to signals suitable for transmission over the bus

lines.

6.7.1.2

Lowpower/Off modes

The CAN transceiver will be in Lowpower mode with bus wake-up detection enabled if bit

STBCC = 1 (see Table 6). The CAN transceiver can be woken up remotely via pins CANH

and CANL in Lowpower mode.

When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the CAN transceiver

will be in Off mode if bit STBCC = 0. The CAN transceiver is powered down completely in

Off mode to minimize quiescent current consumption.

A filter at the receiver input prevents unwanted wake-up events occurring due to

automotive transients or EMI.

A recessive-dominant-recessive-dominant sequence must occur on the CAN bus within

the wake-up timeout time (tto(wake)) to pass the wake-up filter and trigger a wake-up event

(see Figure 9; note that additional pulses may occur between the recessive/dominant

phases). The minimum recessive/dominant bus times for CAN transceiver wake-up

(twake(busrec)min and twake(busdom)min) must be satisfied (see Table 11).

Fig 9.

CAN wake-up timing diagram

recessive

dominant

recessive

dominant

wake-up

015aaa107

twake < tto(wake)

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