PIC24F04KA201 datasheet(121/224 Pages) MICROCHIP

121 / 224 page

Preliminary

DS39937B-page 119

PIC24F04KA201 FAMILY

To set up the SPI module for the Enhanced Buffer

Master (EBM) mode of operation:

If using interrupts:

Clear the respective SPI1IF bit in the IFS0

Set the respective SPI1IE bit in the IEC0

Write the respective SPI1IPx bits in the

IPC2 register.

Write the desired settings to the SPI1CON1

and SPI1CON2 registers with the MSTEN bit

(SPI1CON1<5>) = 1.

Clear the SPIROV bit (SPI1STAT<6>).

Select Enhanced Buffer mode by setting the

SPIBEN bit (SPI1CON2<0>).

Enable SPI operation by setting the SPIEN bit

(SPI1STAT<15>).

Write the data to be transmitted to the SPI1BUF

as soon as data is written to the SPI1BUF

To set up the SPI module for the Enhanced Buffer

Slave mode of operation:

Clear the SPI1BUF register.

If using interrupts:

a) Clear the respective SPI1IF bit in the IFS0

b) Set the respective SPI1IE bit in the IEC0

Write the respective SPI1IPx bits in the

IPC2 register to set the interrupt priority.

Write the desired settings to the SPI1CON1 and

SPI1CON2 registers with the MSTEN bit

(SPI1CON1<5>) = 0.

Clear the SMP bit.

If the CKE bit is set, then the SSEN bit must be

set, thus enabling the SS1 pin.

Clear the SPIROV bit (SPI1STAT<6>).

Select Enhanced Buffer mode by setting the

SPIBEN bit (SPI1CON2<0>).

Enable SPI operation by setting the SPIEN bit

(SPI1STAT<15>).

FIGURE 15-2:

SPI1 MODULE BLOCK DIAGRAM (ENHANCED BUFFER MODE)

Internal Data Bus

SDI1

SDO1

SS1/FSYNC1

SCK1

SPI1SR

bit 0

Shift Control

Edge

Select

FCY

Enable

Sync

SPI1BUF

Control

Transfer

Write SPI1BUF

Read SPI1BUF

SPI1CON1<1:0>

SPI1CON1<4:2>

Master Clock

8-Level FIFO

Transmit Buffer

8-Level FIFO

Receive Buffer

Clock

Control

Primary

1:1/4/16/64

Prescaler

Secondary

Prescaler

1:1 to 1:8

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