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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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PIC24F04KA201 bảng dữ liệu(PDF) 32 Page - Microchip Technology |
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PIC24F04KA201 bảng dữ liệu(HTML) 32 Page - Microchip Technology |
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32 / 224 page  TABLE 4-4: ICN REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CNEN1 0060 — CN14IE(1) CN13IE(1) CN12IE CN11IE — — CN8IE — CN6IE(1) CN5IE(1) CN4IE(1) CN3IE CN2IE CN1IE CN0IE 0000 CNEN2 0062 — CN30IE CN29IE — — — — —CN23IE(1) CN22IE CN21IE — — — — — 0000 CNPU1 0068 —CN14PUE(1) CN13PUE(1) CN12PUE CN11PUE — —CN8PUE — CN6PUE(1) CN5PUE(1) CN4PUE(1) CN3PUE CN2PUE CN1PUE CN0PUE 0000 CNPU2 006A — CN30PUE CN29PUE — — — — — CN23PUE(1) CN22PUE CN21PUE — — — — — 0000 CNPD1 0070 —CN14PDE(1) CN13PDE(1) CN12PDE CN11PDE — —CN8PDE — CN6PDE(1) CN5PDE(1) CN4PDE(1) CN3PDE CN2PDE CN1PDE CN0PDE 0000 CNPD2 0072 — CN30PDE CN29PDE — — — — — CN23PDE(1) CN22PDE CN21PDE — — — — — 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: These bits are not implemented on 14-pin devices. TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 INTCON2 0082 ALTIVT DISI — — — — — — — — — — — INT2EP INT1EP INT0EP 0000 IFS0 0084 NVMIF — AD1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF — — — T1IF OC1IF IC1IF INT0IF 0000 IFS1 0086 — —INT2IF — — — — — — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 IFS3 008A — — — — — — — — — — — — — — — — 0000 IFS4 008C — —CTMUIF — — — —HLVDIF — — — — — —U1ERIF — 0000 IEC0 0094 NVMIE — AD1IE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE — — — T1IE OC1IE IC1IE INT0IE 0000 IEC1 0096 — —INT2IE — — — — — — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 IEC3 009A — — — — — — — — — — — — — — — — 0000 IEC4 009C — —CTMUIE — — — —HLVDIE — — — — — —U1ERIE — 0000 IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 IPC1 00A6 — T2IP2 T2IP1 T2IP0 — — — — — — — — — — — — 4444 IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 SPF1IP0 —T3IP2 T3IP1 T3IP0 4444 IPC3 00AA — NVMIP2 NVMIP1 NVMIP0 — — — — — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 4044 IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 4444 IPC5 00AE — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004 IPC7 00B2 — — — — — — — — — INT2IP2 INT2IP1 INT2IP0 — — — — 4440 IPC16 00C4 — — — — — — — — — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4440 IPC18 00C8 — — — — — — — — — — — — — HLVDIP2 HLVDIP1 HLVDIP0 0004 IPC19 00CA — — — — — — — — — CTMUIP2 CTMUIP1 CTMUIP0 — — — — 0040 INTTREG 00E0 CPUIRQ —VHOLD — ILR3 ILR2 ILR1 ILR0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. |
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