PIC16F707-ESLASHML datasheet(97/284 Pages) MICROCHIP

97 / 284 page

 2010 Microchip Technology Inc.

Preliminary

DS41418A-page 97

PIC16F707/PIC16LF707

OPTION_REG: OPTION REGISTER

R/W-1

RBPU

INTEDG

TMR0CS

TMR0SE

PSA

PS2

PS1

PS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual PORT latch values

bit 6

INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin

0 = Interrupt on falling edge of INT pin

bit 5

TMR0CS: TMR0 Clock Source Select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (FOSC/4)

bit 4

TMR0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3

PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0

PS<2:0>: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

BIT VALUE

TMR0 RATE

WDT RATE

TABLE 12-1:

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE

PEIE

TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

0000 000x 0000 000x

OPTION_REG

RBPU

INTEDG

TMR0CS

TMR0SE

PSA

PS2

PS1

PS0

1111 1111 1111 1111

TMR0

Timer0 Module Register

xxxx xxxx uuuu uuuu

TRISA

TRISA7

TRISA6

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

1111 1111 1111 1111

Legend:

– = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.

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