HT68F03 datasheet(24/139 Pages) HOLTEK

24 / 139 page

HT66F03/HT66F04/HT68F03/HT68F04

Rev. 1.00

April 16, 2010

· EEC Register

Bit

76543210

Name

¾¾¾¾

WREN

RDEN

R/W

¾¾¾¾

R/W

POR

¾¾¾¾

0000

Bit7~4

Unimplemented, read as

²0²

Bit 3

WREN: Data EEPROM Write Enable

0: Disable

1: Enable

This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write

operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations.

Bit 2

WR: EEPROM Write Control

0: Write cycle has finished

1: Activate a write cycle

This is the Data EEPROM Write Control Bit and when set high by the application program will

activate a write cycle. This bit will be automatically reset to zero by the hardware after the write

cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high.

Bit 1

RDEN: Data EEPROM Read Enable

0: Disable

1: Enable

This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read

operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations.

Bit 0

RD: EEPROM Read Control

0: Read cycle has finished

1: Activate a read cycle

This is the Data EEPROM Read Control Bit and when set high by the application program will

activate a read cycle. This bit will be automatically reset to zero by the hardware after the read

cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high.

Note: The WREN, WR, RDEN and RD can not be set to

²1² at the same time in one instruction. The WR and RD can

not be set to

²1² at the same time.

· EED Register

Bit

76543210

Name

R/W

POR

xxxxxxxx

²x² unknown

Bit7~0

Data EEPROM address

Data EEPROM address bit 7 ~ bit 0

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