SC68C652B datasheet(6/43 Pages) NXP

6 / 43 page

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

6 of 43

NXP Semiconductors

SC68C652B

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

RESET

Reset (active LOW). This pin will reset the internal registers and

all the outputs. The UART transmitter output and the receiver input

will be disabled during reset time. See Section 7.11 “SC68C652B

external reset condition” for initialization details.

RIA

Ring Indicator (active LOW). These inputs are associated with

individual UART channels A and B. A logic 0 on these pins

indicates the modem has received a ringing signal from the

telephone line. A logic 1 transition on these input pins generates an

interrupt.

RIB

RTSA

Request to Send (active LOW). These outputs are associated

with individual UART channels, A and B. A logic 0 on the RTSn pin

indicates the transmitter has data ready and waiting to send.

Writing a logic 1 in the modem control register MCR[1] will set this

pin to a logic 0, indicating data is available. After a reset these pins

are set to a logic 1. These pins have no effect on the UART’s

transmit or receive operation.

RTSB

RXA

Receive data input. These inputs are associated with individual

serial channel data to the SC68C652B receive input circuits A and

B. The RXn pin will be a logic 1 during reset, idle (no data), or when

the transmitter is disabled. During the local loopback mode, these

RXn input pins are disabled and transmit data is connected to the

UART receive input internally.

RXB

RXRDYA31

Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW

when the trigger level has been reached or the FIFO has at least

one character. It goes HIGH when the receive FIFO is empty.

RXRDYB

TXA

Transmit data A, B. These outputs are associated with individual

serial transmit channel data from the SC68C652B. The TXn pin will

be a logic 1 during reset, idle (no data), or when the transmitter is

disabled. During the local loopback mode, the TXn output pins are

disabled and transmit data is internally connected to the UART

receive input.

TXB

TXRDYA43

Transmit Ready A, B (active LOW). These outputs provide the

transmit FIFO/THR status for individual transmit channels A and B.

TXRDYn is primarily intended for monitoring DMA mode 1 transfers

for the transmit data FIFOs. An individual channel’s TXRDYA,

TXRDYB buffer ready status is indicated by logic 0, that is, at least

one location is empty and available in the FIFO or THR. This pin

goes to a logic 1 (DMA mode 1) when there are no more empty

locations in the FIFO or THR. This signal can also be used for

single mode transfers (DMA mode 0).

TXRDYB

Table 2.

Pin description …continued

Symbol

Type

Description

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