SC68C652B datasheet(5/43 Pages) NXP

5 / 43 page

SC68C652B_2

Product data sheet

Rev. 02 — 2 November 2009

5 of 43

NXP Semiconductors

SC68C652B

Dual UART with 32-byte FIFOs and IrDA encoder/decoder

CTSA

Clear to Send (active LOW). These inputs are associated with

individual UART channels A and B. A logic 0 (LOW) on the CTSn

pins indicates the modem or data set is ready to accept transmit

data from the SC68C652B. Status can be tested by reading

MSR[4]. These pins have no effect on the UART’s transmit or

receive operation.

CTSB

I/O

Data bus (bidirectional). These pins are the 8-bit, 3-state data

bus for transferring information to or from the controlling CPU. D0 is

the least signiﬁcant bit and the ﬁrst data bit in a transmit or receive

serial data stream.

I/O

DSRA

Data Set Ready (active LOW). These inputs are associated with

individual UART channels A and B. A logic 0 (LOW) on these pins

indicates the modem or data set is powered-on and is ready for

data exchange with the UART. These pins have no effect on the

UART’s transmit or receive operation.

DSRB

DTRA

Data Terminal Ready (active LOW). These outputs are

associated with individual UART channels A and B. A logic 0

(LOW) on these pins indicates that the SC68C652B is powered-on

and ready. These pins can be controlled via the modem control

logic 0 (LOW), enabling the modem. The output of these pins will

be a logic 1 after writing a logic 0 to MCR[0], or after a reset. These

pins have no effect on the UART’s transmit or receive operation.

DTRB

GND

17, 24

Signal and power ground

IRQ

Interrupt Request. Interrupts from UART channels A-B are

wire-ORed internally to function as a single IRQ interrupt. This pin

transitions to a logic 0 (if enabled by the interrupt enable register)

whenever a UART channel(s) requires service. Individual channel

interrupt status can be determined by addressing each channel

through its associated internal register, using CS and A3. An

external pull-up resistor must be connected between this pin and

VCC.

R/W

A logic LOW on this pin will transfer the contents of the data bus

(D[7:0]) from an external CPU to an internal register that is deﬁned

by address bits A[2:0]. A logic HIGH on this pin will load the

contents of an internal register deﬁned by address bits A[2:0] on

the SC68C652B data bus (D[7:0]) for access by an external CPU.

n.c.

12, 25,

29, 37

not connected

OP2A

Output 2 (user-deﬁned). This function is associated with

individual channels A and B. The state of these pins is deﬁned by

the user through the software settings of MCR[3]. OP2A/OP2B is a

logic 0 when MCR[3] is set to a logic 1. OP2A/OP2B is a logic 1

when MCR[3] is set to a logic 0. The output of these two pins is

HIGH after reset.

OP2B

Table 2.

Pin description …continued

Symbol

Type

Description

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