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SC68C652B bảng dữ liệu(PDF) 4 Page - NXP Semiconductors

tên linh kiện SC68C652B
Giải thích chi tiết về linh kiện  5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, and 68 mode mP interface
PDF  43 Pages
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nhà sản xuất  NXP [NXP Semiconductors]
Trang chủ  http://www.nxp.com
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SC68C652B bảng dữ liệu(HTML) 4 Page - NXP Semiconductors

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SC68C652B_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 2 November 2009
4 of 43
NXP Semiconductors
SC68C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
5.
Pinning information
5.1 Pinning
5.2 Pin description
Fig 2.
Pin configuration for LQFP48
SC68C652BIB48
D5
RESET
D6
DTRB
D7
DTRA
RXB
RTSA
RXA
OP2A
TXRDYB
RXRDYA
TXA
IRQ
TXB
n.c.
OP2B
A0
CS
A1
A3
A2
n.c.
n.c.
002aab324
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Table 2.
Pin description
Symbol
Pin
Type
Description
A0
28
I
Address 0 select bit. Internal registers address selection.
A1
27
I
Address 1 select bit. Internal registers address selection.
A2
26
I
Address 2 select bit. Internal registers address selection.
A3
11
I
Address 3 select bit. A3 is used to select Channel A or
Channel B. A logic LOW selects Channel A, and a logic HIGH
selects Channel B. (See Table 3.)
CDA40
I
Carrier Detect (active LOW). These inputs are associated with
individual UART channels A and B. A logic 0 on these pins
indicates that a carrier has been detected by the modem for that
channel.
CDB
16
I
CS
10
I
Chip Select (active LOW). This pin enables data transfers
between the user CPU and the SC68C652B for the channel(s)
addressed. Individual UART sections (A, B) are addressed by A3.
See Table 3.



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