SC28L92 datasheet(13/73 Pages) NXP

13 / 73 page

SC28L92_7

Product data sheet

Rev. 07 — 19 December 2007

13 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

[1]

HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply

ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be

soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias

need to be incorporated in the PCB in the thermal pad region.

Functional description

6.1 Block diagram

The SC28L92 DUART consists of the following eight major sections: data bus buffer,

operation control, interrupt control, timing, communications channels A and B, input port

and output port. Refer to Section 4 “Block diagram”.

6.1.1 Data bus buffer

The data bus buffer provides the interface between the external and internal data buses. It

is controlled by the operation control block to allow read and write operations to take place

between the controlling CPU and the DUART.

6.1.2 Operation control

The operation control logic receives operation commands from the CPU and generates

appropriate signals to internal sections to control device operation. It contains address

decoding and read and write circuits to permit communications with the microprocessor

via the data bus.

6.1.3 Interrupt control

A single active LOW interrupt output (INTRN) is provided which is activated upon the

occurrence of any of eight internal events. Associated with the interrupt system are the

Interrupt Mask Register (IMR) and the Interrupt Status Register (ISR). The IMR can be

programmed to select only certain conditions to cause INTRN to be asserted. The ISR

can be read by the CPU to determine all currently active interrupting conditions. Outputs

OP3 to OP7 can be programmed to provide discrete interrupt outputs for the transmitter,

IP3

Input 3: General purpose input or channel A transmitter external clock

input (TxCA). When the external clock is used by the transmitter, the

transmitted data is clocked on the falling edge of the clock.

IP4

Input 4: General purpose input or channel A receiver external clock

input (RxCA). When the external clock is used by the receiver, the

received data is sampled on the rising edge of the clock.

IP5

Input 5: General purpose input or channel B transmitter external clock

input (TxCB). When the external clock is used by the transmitter, the

transmitted data is clocked on the falling edge of the clock.

VCC

38, 39

Pwr

Power Supply: 3.3 V

± 10 % or 5 V ± 10 % supply input.

GND

16, 17

18[1]

Pwr

Ground

n.c.

1, 23, 34

6, 13, 24,

25, 36, 37,

Not connected

Table 3.

Pin description for 68xxx bus interface (Motorola) …continued

Symbol

Type

Description

PLCC44

QFP44

HVQFN48

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