SC28L92 datasheet(5/73 Pages) NXP

5 / 73 page

SC28L92_7

Product data sheet

Rev. 07 — 19 December 2007

5 of 73

NXP Semiconductors

SC28L92

3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter

The data pins TxD and RxD are considered idle at the logic 1 (HIGH) level when inactive, or active when at the logic 0

(LOW) level. Comments about these levels when RS232 is referenced often refer to Mark and Space levels. Mark usually

means inactive and Space means active. The voltage levels represented by the terms Mark and Space are often reversed

from those above: Mark is low voltage, and Space is high voltage.

Fig 2.

Block diagram (68xxx mode)

SC28L92 (68xxx mode)

002aad460

BUS BUFFER

CHANNEL B

(AS ABOVE)

D0 to D7

OPERATION

CONTROL

ADDRESS

DECODE

R/W CONTROL

RESETN

I/M

ground for

68xxx mode

A0 to A3

CEN

IACKN

R/WN

INTERRUPT

CONTROL

IMR

ISR

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

COUNTER/

TIMER

XTAL

OSCILLATOR

CSRA

CSRB

ACR

CTL

CTU

INTRN

X1/CLK

CHANNEL A

16-BYTE

TRANSMIT FIFO

TRANSMIT

SHIFT REGISTER

16-BYTE

RECEIVE FIFO

WATCHDOG

TIMER

TxDA

RxDA

RxDB

RECEIVE

SHIFT REGISTER

MRA0, 1, 2, 3

CRA

SRA

INPUT PORT

CHANGE-OF-

STATE

DETECTORS (4)

ACR

IPCR

IP0 to IP5

TxDB

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPR

OPCR

OP0 to OP7

DACKN

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