SC16IS752IPW datasheet(49/59 Pages) NXP

49 / 59 page

SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 — 19 May 2008

49 of 59

NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 39.

SPI-bus timing speciﬁcations

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;

VDD = 2.5 V ± 0.2 V, Tamb = −40 °Cto+85 °C; or VDD = 3.3 V ± 0.3 V, Tamb = −40 °Cto+95 °C; VIL and VIH refer to input

voltage of VSS to VDD. All output load = 25 pF, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

VDD = 2.5 V

VDD = 3.3 V

Unit

Min

Max

Min

Max

tTR

CS HIGH to SO 3-state

CL = 100 pF

100

tCSS

CS to SCLK setup time

100

tCSH

CS to SCLK hold time

tDO

SCLK fall to SO valid delay time

CL = 100 pF

tDS

SI to SCLK setup time

tDH

SI to SCLK hold time

tCP

SCLK period

tCL + tCH

tCH

SCLK HIGH time

tCL

SCLK LOW time

tCSW

CS HIGH pulse width

200

td9

SPI output data valid time

200

td10

SPI modem output data valid time

200

td11

SPI transmit interrupt clear time

200

td12

SPI modem input interrupt clear time

200

td13

SPI interrupt clear time

200

td14

SPI receive interrupt clear time

200

tw(rst)

reset pulse width

µs

Fig 30. Detailed SPI-bus timing

tCSH

tCSS

tCL

tCH

tCSH

tDO

tTR

tDS

tDH

SCLK

002aab066

tCSW

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