P89LPC985FDH datasheet(12/85 Pages) NXP

12 / 85 page

P89LPC980_982_983_985_2

Preliminary data sheet

Rev. 02 — 8 February 2010

12 of 85

NXP Semiconductors

P89LPC980/982/983/985

8-bit microcontroller with accelerated two-clock 80C51 core

P1.7/AD04/T3EX/

MOSI

4I/O

P1.7 — Port 1 bit 7. High current source.

AD04 — ADC0 channel 4 analog input. (P89LPC985)

T3EX — Timer/counter 3 external capture input.

I/O

MOSI — SPI master out slave in. When configured as master, this pin is output;

when configured as slave, this pin is input. (pin remap)

P2.0 to P2.7

I/O

Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset

Port 2 latches are configured in the input only mode with the internal pull-up

disabled. The operation of Port 2 pins as inputs and outputs depends upon the port

configuration selected. Each port pin is configured independently. Refer to Section

7.16.1 “Port configurations” and Table 13 “Static characteristics” for details.

All pins have Schmitt trigger inputs.

Port 2 also provides various special functions as described below:

P2.0/AD07/TXD

I/O

P2.0 — Port 2 bit 0.

AD07 — ADC0 channel 7 analog input. (P89LPC985)

TXD — Transmitter output for serial port. (pin remap)

P2.1/AD06/RXD

I/O

P2.1 — Port 2 bit 1.

AD06 — ADC0 channel 6 analog input. (P89LPC985)

RXD — Receiver input for serial port. (pin remap)

P2.2/MOSI

I/O

P2.2 — Port 2 bit 2.

I/O

MOSI — SPI master out slave in. When configured as master, this pin is output;

when configured as slave, this pin is input.

P2.3/MISO

I/O

P2.3 — Port 2 bit 3.

I/O

MISO — SPI master in slave out.When configured as master, this pin is input,

when configured as slave, this pin is output.

P2.4/SS

I/O

P2.4 — Port 2 bit 4.

SS — SPI Slave select.

P2.5/SPICLK

I/O

P2.5 — Port 2 bit 5.

I/O

SPICLK — SPI clock. When configured as master, this pin is output; when

configured as slave, this pin is input.

P2.6/SCL

I/O

P2.6 — Port 2 bit 6.

I/O

SCL — I2C-bus serial clock input/output. (pin remap)

P2.7/SDA

I/O

P2.7 — Port 2 bit 7.

I/O

SDA — I2C-bus serial data input/output. (pin remap)

P3.0 to P3.1

I/O

Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset

Port 3 latches are configured in the input only mode with the internal pull-up

disabled. The operation of Port 3 pins as inputs and outputs depends upon the port

configuration selected. Each port pin is configured independently. Refer to Section

7.16.1 “Port configurations” and Table 13 “Static characteristics” for details.

All pins have Schmitt trigger inputs.

Port 3 also provides various special functions as described below:

Table 3.

Pin description …continued

Symbol

Type

Description

PLCC28,

TSSOP28

P89LPC985FDH bảng dữ liệu(PDF) 12 Page - NXP Semiconductors

P89LPC985FDH bảng dữ liệu(HTML) 12 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

bảng dữ liệu tải về

Link URL