P89LPC985FDH datasheet(58/85 Pages) NXP

58 / 85 page

P89LPC980_982_983_985_2

Preliminary data sheet

Rev. 02 — 8 February 2010

58 of 85

NXP Semiconductors

P89LPC980/982/983/985

8-bit microcontroller with accelerated two-clock 80C51 core

Remark: Users who wish to use this loader should take precautions to avoid erasing the

1 kB sector that contains this bootloader. Instead, the page erase function can be used to

erase the first eight 64-byte pages located in this sector.

A custom bootloader can be written with the Boot Vector set to the custom bootloader, if

desired.

7.29.10 Hardware activation of the bootloader

The bootloader can also be executed by forcing the device into ISP mode during a

power-on sequence (see the P89LPC980/982/983/985 User manual for specific

information). This has the same effect as having a non-zero status byte. This allows an

application to be built that will normally execute user code but can be manually forced into

ISP operation. If the factory default setting for the boot is changed, it will no longer point to

the factory pre-programmed ISP bootloader code. After programming the flash, the status

byte should be programmed to zero in order to allow execution of the user’s application

code beginning at address 0000H.

7.30 User configuration bytes

Some user-configurable features of the P89LPC980/982/983/985 must be defined at

power-up and therefore cannot be set by the program after start of execution. These

features are configured through the use of the flash byte UCFG1 and UCFG2. Please see

the P89LPC980/982/983/985 User’s Manual for additional details.

7.31 User sector security bytes

There are four/eight User Sector Security Bytes on the P89LPC980/982/983/985. Each

byte corresponds to one sector. Please see the P89LPC980/982/983/985 User manual for

additional details.

ADC (P89LPC983/985)

8.1 General description

The P89LPC985 has a 10-bit, 8-channel multiplexed successive approximation

analog-to-digital converter modules. The P89LPC983 has a 10-bit, 4-channel multiplexed

successive approximation analog-to-digital converter modules. A block diagram of the

ADC is shown in Figure 20 “ADC block diagram”.

Table 11.

Default boot vector values and ISP entry points

Device

Default

boot vector

Default

bootloader

entry point

Default bootloader

code range

1 kB sector

range

P89LPC980

0FH

0F00H

0E00H to 0FFFH

0C00H to 0FFFH

P89LPC982

1FH

1F00H

1E00H to 1FFFH

1C00H to 1FFFH

P89LPC983

0FH

0F00H

0E00H to 0FFFH

0C00H to 0FFFH

P89LPC985

1FH

1F00H

1E00H to 1FFFH

1C00H to 1FFFH

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