LPC2362 datasheet(13/57 Pages) NXP

13 / 57 page

LPC2361_62_4

Product data sheet

Rev. 04 — 4 March 2010

13 of 57

NXP Semiconductors

LPC2361/62

Single-chip 16-bit/32-bit MCU

[3]

5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,

digital section of the pad is disabled.

[4]

Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide

output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

Open-drain configuration applies to all functions on this pin.

[5]

Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and

Low-speed mode only).

[6]

5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[7]

5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[8]

Pad provides special analog functionality.

[9]

When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

[10] Pad provides special analog functionality.

[11] Pad provides special analog functionality.

[12] Pad provides special analog functionality.

[13] Pad provides special analog functionality.

[14] Pad provides special analog functionality.

Functional description

7.1 Architectural overview

The LPC2361/2362 microcontroller consists of an ARM7TDMI-S CPU with emulation

support, the ARM7 local bus for closely coupled, high-speed access to the majority of

on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals, and the

AMBA APB for connection to other on-chip peripheral functions. The microcontroller

permanently configures the ARM7TDMI-S processor for little-endian byte order.

The LPC2362 implements two AHBs in order to allow the Ethernet block to operate

without interference caused by other system activity. The primary AHB, referred to as

AHB1, includes the VIC and GPDMA controller.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,

and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2

are the ARM7 and the Ethernet block.

AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB

ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the

AHB address space. Lower speed peripheral functions are connected to the APB. The

AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a

2 MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is

allocated a 16 kB address space within the APB address space.

The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers

high performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

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