LPC2362 datasheet(21/57 Pages) NXP

21 / 57 page

LPC2361_62_4

Product data sheet

Rev. 04 — 4 March 2010

21 of 57

NXP Semiconductors

LPC2361/62

Single-chip 16-bit/32-bit MCU

7.11.1 Features

• Two CAN controllers and buses.

• Data rates to 1 Mbit/s on each bus.

• 32-bit register and RAM access.

• Compatible with CAN specification 2.0B, ISO 11898-1.

• Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN

buses.

• Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard Identifiers.

• FullCAN messages can generate interrupts.

7.12 10-bit ADC

The LPC2361/2362 contain one ADC. It is a single 10-bit successive approximation ADC

with six channels.

7.12.1 Features

• 10-bit successive approximation ADC.

• Input multiplexing among 6 pins.

• Power-down mode.

• Measurement range 0 V to Vi(VREF).

• 10-bit conversion time ≥ 2.44 μs.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or Timer Match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

7.13 10-bit DAC

The DAC allows the LPC2361/2362 to generate a variable analog output. The maximum

output value of the DAC is Vi(VREF).

7.13.1 Features

• 10-bit DAC

• Resistor string architecture

• Buffered output

• Power-down mode

• Selectable output drive

7.14 UARTs

The LPC2361/2362 each contain four UARTs. In addition to standard transmit and receive

data lines, UART1 also provides a full modem control handshake interface.

The UARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

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