DM9102DEP datasheet(27/70 Pages) DAVICOM

27 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

IAFM

0,RO

Inverse Address Filtering Mode

It is set to indicate the DM9102D operate in Inverse filtering mode. This is a read

only bit and decoded from the setup frame of TDES1 bit 28 and bit 22.

PBF

0,RW

Pass Bad Frame

When set, the DM9102 is indicated that receiving the bad frames, including runt

packets and truncated frames, is caused by the FIFO overflow. The bad frame also

has to pass the address filtering if the DM9102D is not set in promiscuous mode.

HOFM

0,RO

Hash-only Filter Mode

It is set to indicate the DM9102D operate in Hash-only filtering mode. This is a read

only bit and decoded from the setup frame of TDES1 bit 28 and bit 22.

RXRC

0,RW

Receive Start/Stop Command

When set, receive process will begin by fetching the receive descriptor for available

buffer to store the new-coming packet (placed in the running state). If the fetched

descriptor is owned by the host (no descriptor is owned by the DM9102D), the

receive process will enter the suspend state and receive buffer unavailable

CR5<7> sets. Otherwise it runs to wait for the packet’s incoming. When reset,

receive process is placed in the stopped state after completing the reception of the

current frame.

HPFM

0,RO

Hash/Perfect Filter Mode

It is set to indicate the DM9102D operate in Hash-only or Hash filtering mode and it

is cleared to indicate the DM9102D operate in Perfect filtering mode. This is a read

only bit and decoded from the setup frame of TDES1 bit 28 and bit 22.

6.2.8 Interrupt Mask Register (CR7)

Bit

Name

Default

Description

NISE

0,RW

Normal Interrupt Summary Enable

This bit is set to enable the interrupt for Normal Interrupt Summary.

Normal interrupt includes three conditions:

CR5<0> – TXCI: Transmit Complete Interrupt

CR5<2> – TXDU: Transmit Buffer Unavailable

CR5<6> – RXCI: Receive Complete Interrupt

AISE

0,RW

Abnormal Interrupt Summary Enable

This bit is set to enable the interrupt for Abnormal Interrupt Summary.

Abnormal interrupt includes all interrupt conditions as shown below, excluding

Normal Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5),

RXDU(bit7), RXPS(bit8), RXWT(bit9), SBE(bit13).

Reserved

0,RO

Reserved

SBEE

0,RW

System Bus Error Enable

When set together with CR7<15>, CR5<13>, it enables the interrupt for System

Bus Error. The type of system bus error is shown in CR5<24:23>.

LINKE

0,RW

Link Change Interrupt Enable

When this bit and CR7<16>, CR5<12> are set together, it will enable the interrupt

of link status changed condition.

11:10

Reserved

0,RO

Reserved

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