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AS3524 bảng dữ liệu(PDF) 58 Page - ams AG |
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AS3524 bảng dữ liệu(HTML) 58 Page - ams AG |
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58 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 58 - 124 Table 38 I2S output raw status register Name Base Default I2SOUT_RAW_STATUS AS3525_I2SOUT_BASE 0x00 Raw status register Offset: 0x0008 The read-only raw status register contains the actual bit values as reflected by the FIFO controller status signals. I2SOUT_POER and I2SOUT_PUER are static bits, since FIFO controller gives the PUSH/POP error bit only for one clock. This means that these two bits remain asserted until they are cleared in the I2SOUT_CLEAR register. All other bits change state depending on the underlying logic, i.e. state of FIFO controller. Bit Bit Name Default Access Bit Description 7 stereo18_status 0 R Status of write interface for 18 bit stereo mode 0: left audio sample is expected next 1: right audio sample is expected next 6 I2SOUT_POER 0 R 1 if FIFO POP error 5 I2SOUT_PUE 0 R 1 if FIFO PUSH is empty 4 I2SOUT_PUAE 0 R 1 if FIFO PUSH is almost empty 3 I2SOUT_PUHF 0 R 1 if FIFO PUSH is half full 2 I2SOUT_PUAF 0 R 1 if FIFO PUSH is almost full 1 I2SOUT_PUF 0 R 1 if FIFO PUSH is full 0 I2SOUT_PUER 0 R 1 if FIFO PUSH error Table 39 I2S output status register Name Base Default I2SOUT_STATUS AS3525_I2SOUT_BASE 0x00 Status register Offset: 0x000C The status register is a read-only register. A read to this register returns the value of the raw status bits AND’ed with the corresponding mask of enable bits set in the mask register. Bit Bit Name Default Access Bit Description 7 stereo18_status 0 R Status of write interface for 18 bit stereo mode 0: left audio sample is expected next 1: right audio sample is expected next 6 I2SOUT_POER 0 R 1 if FIFO POP error 5 I2SOUT_PUE 0 R 1 if FIFO PUSH is empty 4 I2SOUT_PUAE 0 R 1 if FIFO PUSH is almost empty 3 I2SOUT_PUHF 0 R 1 if FIFO PUSH is half full 2 I2SOUT_PUAF 0 R 1 if FIFO PUSH is almost full 1 I2SOUT_PUF 0 R 1 if FIFO PUSH is full 0 I2SOUT_PUER 0 R 1 if FIFO PUSH error |
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