AS3524 datasheet(84/124 Pages) AMSCO

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AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

5.3.13.1 UART Baud Generator and Clock Divider Settings

The internal baud generator module generates the required baud clock using the divisor register value. To achieve correct synchronizationincoming

bits are over sampled by a factor of 16x. Software should program the divisor value by which the system clock has to be divided to achieve the

required baud clock frequency.

The equation to calculate baud divisor is

Baud Divisor = (input frequency)

÷ (baud rate x 16)

Important: the internal clock divider must be set to a value of 2 or higher. Setting the value to 1 (no division) is not allowed!

For example, for 16 MHz PCLK clock following table gives the list of settings for different BAUD rates.

Baud Rate

Required Baud

clock frequency

Decimal

divisor value

800

20000

1200

13333

110

1760

9091

134.5

2152

7435

150

2400

6667

300

4800

3333

600

9600

1667

1200

19200

833

1800

28800

556

2000

32000

500

4800

76800

208

7200

115200

139

9600

153600

104

19200

307200

38400

614400

56000

896000

128000

204800

250000

4000000

300000

4800000

500000

8000000

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