HT56R656 datasheet(73/108 Pages) HOLTEK

73 / 108 page

HT56R62/HT56R65

HT56R642/HT56R644/HT56R654/HT56R656

Rev. 1.00

July 20, 2009

nal peripheral interrupt pin is pin-shared with one of the

segment pins, and is configured as a peripheral interrupt

pin via a configuration option. When the interrupt is en-

abled, the stack is not full and a negative transition type

appears on the external peripheral interrupt pin, a sub-

routine call to the Multi-function interrupt vector at

location18H, will take place. When the external periph-

eral interrupt is serviced, the EMI bit will be cleared to

disable other interrupts, however only the MFF interrupt

request flag will be reset. As the PEF flag will not be au-

tomatically reset, it has to be cleared by the application

program.

Timer/Event Counter Interrupt

For a Timer/Event Counter 0 or Timer/Event Counter 1

interrupt to occur, the global interrupt enable bit, EMI,

and the corresponding timer interrupt enable bit, ET0I or

ET1I must first be set. An actual Timer/Event Counter in-

terrupt will take place when the Timer/Event Counter re-

quest flag, T0F or T1F is set, a situation that will occur

when the Timer/Event Counter overflows. When the in-

terrupt is enabled, the stack is not full and a Timer/Event

Counter overflow occurs, a subroutine call to the timer

interrupt vector at location 0CH or 10C, will take place.

When the interrupt is serviced, the timer interrupt re-

quest flag, T0F or T1F, will be automatically reset and

the EMI bit will be automatically cleared to disable other

interrupts.

Timer Event Counter 0 and Timer/Event Counter 1 have

their own individual interrupt vectors, however the inter-

rupt vector for Timer/Event Counter 2 is contained within

the Multi-function Interrupt. For a Timer/Event Counter 2

interrupt to occur, the global interrupt enable bit, EMI,

Timer/Event Counter 2 interrupt enable bit, ET2I, and

Multi-function interrupt enable bit, EMFI, must first be

set. An actual external peripheral interrupt will take

place when the Timer/Event Counter 2 request flag,

T2F, is set, a situation that will occur when the

Timer/Event Counter 2 overflows. When the interrupt is

enabled, the stack is not full and the Timer/Event Coun-

ter 2 overflows, a subroutine call to the Multi-function in-

terrupt vector at location 18H, will take place. When the

Timer/Event 2 interrupt is serviced, the EMI bit will be

cleared to disable other interrupts, however only the

MFF interrupt request flag will be reset. As the T2F flag

will not be automatically reset, it has to be cleared by the

application program.

A/D Interrupt

The A/D Interrupt is contained within the Multi-function

Interrupt.

For an A/D Interrupt to be generated, the global interrupt

enable bit, EMI, A/D Interrupt enable bit, EADI, and

Multi-function interrupt enable bit, EMFI, must first be

set. An actual A/D Interrupt will take place when the A/D

Interrupt request flag, ADF, is set, a situation that will oc-

cur when the A/D conversion process has finished.

When the interrupt is enabled, the stack is not full and

the A/D conversion process has ended, a subroutine

call to the Multi-function interrupt vector at location18H,

will take place. When the A/D Interrupt is serviced, the

EMI bit will be cleared to disable other interrupts, how-

ever only the MFF interrupt request flag will be reset. As

the ADF flag will not be automatically reset, it has to be

cleared by the application program.

SPI/I

2C Interface Interrupt

For an SPI/I

2C interrupt to occur, the global interrupt en-

able bit, EMI, and the corresponding interrupt enable bit,

ESIM must be first set. An actual SPI/I

2C interrupt will

take place when the SPI/I

2C interrupt request flag,

SIMF, is set, a situation that will occur when a byte of

data has been transmitted or received by the SPI/I

2Cin-

terface or when an I

2C address match occurs. When the

interrupt is enabled, the stack is not full and a byte of

data has been transmitted or received by the SPI/I

2Cin-

terface or an I

2C address match occurs, a subroutine

call to the SPI/I

2C interrupt vector at location 14H, will

take place. When the interrupt is serviced, the SPI/I

request flag, SIMF will be automatically reset and the

EMI bit will be automatically cleared to disable other in-

terrupts.

I N T E D G E R e g i s t e r

I N T 0 E d g e S e l e c t

I N T 0 S 1

I N T 0 S 0

I N T 1 E d g e S e l e c t

I N T 1 S 1

I N T 1 S 0

N o t i m p l e m e n t e d , r e a d a s " 0 "

b 0

I N T 1 S 0 I N T 0 S 1 I N T 0 S 0

b 7

I N T 1 S 1

d i s a b l e

r i s i n g e d g e t r i g g e r

f a l l i n g e d g e t r i g g e r

d u a l e d g e t r i g g e r

d i s a b l e

r i s i n g e d g e t r i g g e r

f a l l i n g e d g e t r i g g e r

d u a l e d g e t r i g g e r

Interrupt Active Edge Register

- INTEDGE

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