HT56R656 datasheet(67/108 Pages) HOLTEK

67 / 108 page

HT56R62/HT56R65

HT56R642/HT56R644/HT56R654/HT56R656

Rev. 1.00

July 20, 2009

Buzzer

Operating in a similar way to the Programmable Fre-

quency Divider, the Buzzer function provides a means of

producing a variable frequency output, suitable for ap-

plications such as Piezo-buzzer driving or other external

circuits that require a precise frequency generator. The

BZ and BZ pins form a complementary pair, and are

pin-shared with I/O pins, PA0 and PA1. A configuration

option is used to select from one of three buzzer options.

The first option is for both pins PA0 and PA1 to be used

as normal I/Os, the second option is for both pins to be

configured as BZ and BZ buzzer pins, the third option

selects only the PA0 pin to be used as a BZ buzzer pin

with the PA1 pin retaining its normal I/O pin function.

Note that the BZ pin is the inverse of the BZ pin which to-

gether generate a differential output which can supply

more power to connected interfaces such as buzzers.

The buzzer is driven by the internal clock source, , which

then passes through a divider, the division ratio of which

is selected by configuration options to provide a range of

buzzer frequencies from fS/2

2 to f

S/2

9. The clock source

that generates fS, which in turn controls the buzzer fre-

quency, can originate from three different sources, the

32768Hz oscillator, the 32K_INT oscillator or the Sys-

tem oscillator/4, the choice of which is determined by

the fS clock source configuration option. Note that the

buzzer frequency is controlled by configuration options,

which select both the source clock for the internal clock

fS and the internal division ratio. There are no internal

registers associated with the buzzer frequency.

If the configuration options have selected both pins PA0

and PA1 to function as a BZ and BZ complementary pair

of buzzer outputs, then for correct buzzer operation it is

essential that both pins must be setup as outputs by set-

ting bits PAC0 and PAC1 of the PAC port control register

to zero. The PA0 data bit in the PA data register must

also be set high to enable the buzzer outputs, if set low,

both pins PA0 and PA1 will remain low. In this way the

single bit PA0 of the PA register can be used as an on/off

control for both the BZ and BZ buzzer pin outputs. Note

that the PA1 data bit in the PA register has no control

over the BZ buzzer pin PA1.

f S S o u r c e

C o n f i g u r a t i o n

O p t i o n

f S Y S / 4

3 2 7 6 8 H z

3 2 K _ I N T

C o n f i g u r a t i o n O p t i o n

D i v i d e b y 2 2 ~ 2 9

f S

B Z

Buzzer Function

S I M C T L 0 R e g i s t e r

N o t i m p l e m e n t e d , r e a d a s ' 0 "

S P I / I 2 C O n / O f c o n t r o l

1 : e n a b l e

0 : d i s a b l e

P C K c l o c k s e l e c t

P e r i p h e r a l c l o c k e n a b l e

1 : c l o c k a n d o u t p u t e n a b l e

0 : c l o c k a n d o u t p u t d i s a b l e

S P I M a s t e r / S l a v e a n d c l o c k c o n t r o l

- d e s c r i b e d e l s e w h o s e

b 0

C l o c k S o u r c e

f S Y S

f S Y S / 4

f S Y S / 8

T i m e r / E v n e t C o u n t e r 0 ¸ 2

P C K P S C 1

P C K P S C 0

S I M E N

b 7

S I M 1

S I M 0

S I M 2

P C K E N P C K P S C 1 P C K P S C 0

Peripheral Clock Output Control

- SIMCTL0

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