MAXQ3183-RAN+ datasheet(20/102 Pages) MAXIM

20 / 102 page

Low-Power, Multifunction, Polyphase AFE

with Harmonics and Tamper Detect

______________________________________________________________________________________

During an SPI transfer, data is simultaneously transmit-

ted and received over two serial data lines (MISO and

MOSI) with respect to a single serial shift clock (SCLK).

The polarity and phase of the serial shift clock are the

primary components in defining the SPI data transfer

format. The polarity of the serial clock corresponds to

the idle logic state of the clock line and, therefore, also

defines which clock edge is the active edge. To define

a serial shift clock signal that idles in a logic-low state

(active clock edge = rising), the clock polarity select

(CKPOL; R_SPICF.0) bit should be configured to a 0,

while setting CKPOL = 1 causes the shift clock to idle in

a logic-high state (active clock edge = falling). The

phase of the serial clock selects which edge is used to

sample the serial shift data. The clock phase select

(CKPHA; R_SPICF.1) bit controls whether the active or

inactive clock edge is used to latch the data. When

CKPHA is set to a logic 1, data is sampled on the inac-

tive clock edge (clock returning to the idle state). When

CKPHA is set to a logic 0, data is sampled on the active

clock edge (clock transition to the active state).

Together, the CKPOL and CKPHA bits allow four possi-

ble SPI data transfer formats.

Transfers over the SPI interface always start with the

most significant bit and end with the least significant

bit. All SPI data transfers to and from the MAXQ3183

are always 8 bits (one byte) in length. The MAXQ3183

SPI interface does not support 16-bit character lengths.

The default format (upon power-up or system reset) for

the MAXQ3183 SPI interface is represented in

Figure 4a (CKPOL = 0; CKPHA = 0). In this format, the

SCLK CYCLE #

(FOR REFERENCE)

SCLK (CKPOL = 0)

SCLK (CKPOL = 1)

MOSI

(FROM MASTER)

MISO

(FROM SLAVE)

SSEL (TO SLAVE)

MSB

LSB

MSB

*NOT DEFINED BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.

LSB

MSB

LSB

MSB

*NOT DEFINED BUT NORMALLY LSB OF PREVIOUSLY TRANSMITTED CHARACTER.

LSB

SCLK CYCLE #

(FOR REFERENCE)

SCLK (CKPOL = 0)

SCLK (CKPOL = 1)

MOSI

(FROM MASTER)

MISO

(FROM SLAVE)

SSEL (TO SLAVE)

Figure 4b. SPI Interface Timing (CKPHA = 1)

Figure 4a. SPI Interface Timing (CKPHA = 0)

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