ATmega64A datasheet(295/392 Pages) ATMEL

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295

8160C–AVR–07/09

ATmega64A

27. Memory Programming

27.1

Program and Data Memory Lock Bits

The ATmega64A provides six Lock bits which can be left unprogrammed (“1”) or can be pro-

grammed (“0”) to obtain the additional features listed in Table 27-2. The Lock bits can only be

erased to “1” with the Chip Erase command.

Note:

1. “1” means unprogrammed, “0” means programmed

Table 27-1.

Lock Bit Byte(1)

Lock Bit Byte

Bit no

Description

Default Value

–

1 (unprogrammed)

–

1 (unprogrammed)

BLB12

Boot Lock bit

1 (unprogrammed)

BLB11

Boot Lock bit

1 (unprogrammed)

BLB02

Boot Lock bit

1 (unprogrammed)

BLB01

Boot Lock bit

1 (unprogrammed)

LB2

Lock bit

1 (unprogrammed)

LB1

Lock bit

1 (unprogrammed)

Table 27-2.

Lock Bit Protection Modes(2)

Memory Lock Bits

Protection Type

LB Mode

LB2

LB1

No memory lock features enabled.

Further programming of the Flash and EEPROM is disabled in

Parallel and SPI/JTAG Serial Programming mode. The Fuse bits

are locked in both Serial and Parallel Programming mode.(1)

Further programming and verification of the Flash and

EEPROM is disabled in Parallel and SPI/JTAG Serial

Programming mode. The Fuse bits are locked in both Serial and

Parallel Programming mode.(1)

BLB0 Mode

BLB02

BLB01

No restrictions for SPM or LPM accessing the Application

section.

SPM is not allowed to write to the Application section.

SPM is not allowed to write to the Application section, and LPM

executing from the Boot Loader section is not allowed to read

from the Application section. If Interrupt Vectors are placed in

the Boot Loader section, interrupts are disabled while executing

from the Application section.

LPM executing from the Boot Loader section is not allowed to

read from the Application section. If Interrupt Vectors are placed

in the Boot Loader section, interrupts are disabled while

executing from the Application section.

BLB1 Mode

BLB12

BLB11

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