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ATmega64A bảng dữ liệu(PDF) 255 Page - ATMEL Corporation

tên linh kiện ATmega64A
Giải thích chi tiết về linh kiện  8-bit Microcontroller with 64K Bytes In-System Programmable Flash
PDF  392 Pages
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ATmega64A bảng dữ liệu(HTML) 255 Page - ATMEL Corporation

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8160C–AVR–07/09
ATmega64A
Figure 24-2. TAP Controller State Diagram
24.4
TAP Controller
The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-
scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions
depicted in Figure 24-2 depends on the signal present on TMS (shown adjacent to each state
transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test-
Logic-Reset.
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:
• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift
Instruction Register – Shift-IR state. While in this state, shift the four bits of the JTAG
instructions into the JTAG instruction register from the TDI input at the rising edge of TCK.
The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR
Test-Logic-Reset
Run-Test/Idle
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Select-DR Scan
Capture-DR
0
1
0
11
1
00
00
11
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
0
0
1
1



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