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ATmega64A bảng dữ liệu(PDF) 250 Page - ATMEL Corporation

tên linh kiện ATmega64A
Giải thích chi tiết về linh kiện  8-bit Microcontroller with 64K Bytes In-System Programmable Flash
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ATmega64A bảng dữ liệu(HTML) 250 Page - ATMEL Corporation

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8160C–AVR–07/09
ATmega64A
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input clock to the
ADC.
23.9.3
ADCL and ADCH – The ADC Data Register
23.9.3.1
ADLAR = 0
23.9.3.2
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers. If differential
channels are used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
Table 23-5.
ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
000
2
001
2
010
4
011
8
100
16
101
32
110
64
111
128
Bit
15
141312
1110
9
8
0x05 (0x25)
–
–
–
–
–
–
ADC9
ADC8
ADCH
0x04 (0x24)
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
7
654
321
0
Read/Write
RRR
RRR
RR
RRR
RRR
RR
Initial Value
0
0
0
0
0
0
0
0
0
000
000
0
Bit
15
141312
1110
9
8
0x05 (0x25)
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
0x04 (0x24)
ADC1
ADC0
–
–
–
–
–
–
ADCL
7
654
321
0
Read/Write
RRR
RRR
RR
RRR
RRR
RR
Initial Value
0
0
0
0
0
0
0
0
0
000
000
0



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