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ATmega64A bảng dữ liệu(PDF) 231 Page - ATMEL Corporation |
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ATmega64A bảng dữ liệu(HTML) 231 Page - ATMEL Corporation |
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231 / 392 page  231 8160C–AVR–07/09 ATmega64A 22.2 Register Description 22.2.1 SFIOR – Special Function IO Register • Bit 3 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 230. 22.2.2 ACSR – Analog Comparator Control and Status Register • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar- ator. See “Internal Voltage Reference” on page 55. Table 22-1. Analog Comparator Multiplexed Input ACME ADEN MUX2:0 Analog Comparator Negative Input 0 x xxx AIN1 1 1 xxx AIN1 10 000 ADC0 10 001 ADC1 10 010 ADC2 10 011 ADC3 10 100 ADC4 10 101 ADC5 10 110 ADC6 10 111 ADC7 Bit 7 6 5 4 3 2 1 0 0x20 (0x40) TSM – – – ACME PUD PSR2 PSR10 SFIOR Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7654 3210 0x08 (0x28) ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 N/A 0 0000 |
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