ATmega64A datasheet(228/392 Pages) ATMEL

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228

8160C–AVR–07/09

ATmega64A

• Bit 0 – TWIE: TWI Interrupt Enable

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-

vated for as long as the TWINT flag is high.

21.9.3

TWSR – TWI Status Register

• Bits 7:3 – TWS: TWI Status

These five bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different sta-

tus codes are described later in this section. Note that the value read from TWSR contains both

the 5-bit status value and the 2-bit prescaler value. The application designer should mask the

prescaler bits to zero when checking the status bits. This makes status checking independent of

prescaler setting. This approach is used in this datasheet, unless otherwise noted.

• Bit 2 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bits 1:0 – TWPS: TWI Prescaler Bits

These bits can be read and written, and control the bit rate prescaler.

To calculate bit rates, see “Bit Rate Generator Unit” on page 202. The value of TWPS1:0 is used

in the equation.

21.9.4

TWDR – TWI Data Register

In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR

contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.

This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the data register

cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains sta-

ble as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted

in. TWDR always contains the last byte present on the bus, except after a wake-up from a sleep

mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost

bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is

controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.

Bit

7654

3210

(0x71)

TWS7

TWS6

TWS5

TWS4

TWS3

–

TWPS1

TWPS0

TWSR

Read/Write

RRRR

R/W

Initial Value

1111

1000

Table 21-7.

TWI Bit Rate Prescaler

TWPS1

TWPS0

Prescaler Value

Bit

765

4321

(0x73)

TWD7

TWD6

TWD5

TWD4

TWD3

TWD2

TWD1

TWD0

TWDR

Read/Write

R/W

Initial Value

111

1111

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