ATmega64A datasheet(178/392 Pages) ATMEL

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178

8160C–AVR–07/09

ATmega64A

20.3.3

External Clock

External clocking is used by the synchronous slave modes of operation. The description in this

section refers to Figure 20-2 for details.

External clock input from the XCK pin is sampled by a synchronization register to minimize the

chance of meta-stability. The output from the synchronization register must then pass through

an edge detector before it can be used by the Transmitter and Receiver. This process intro-

duces a two CPU clock period delay and therefore the maximum external XCK clock frequency

is limited by the following equation:

Note that f

osc depends on the stability of the system clock source. It is therefore recommended to

add some margin to avoid possible loss of data due to frequency variations.

20.3.4

Synchronous Clock Operation

When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input

(Slave) or clock output (Master). The dependency between the clock edges and data sampling

or data change is the same. The basic principle is that data input (on RxD) is sampled at the

opposite XCK clock edge of the edge the data output (TxD) is changed.

Figure 20-3. Synchronous Mode XCK Timing

The UCPOLn bit UCRSnC selects which XCK clock edge is used for data sampling and which is

used for data change. As Figure 20-3 shows, when UCPOLn is zero the data will be changed at

rising XCK edge and sampled at falling XCK edge. If UCPOLn is set, the data will be changed at

falling XCK edge and sampled at rising XCK edge.

20.4

Frame Formats

A serial frame is defined to be one character of data bits with synchronization bits (start and stop

bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of

the following as valid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit

• 1 or 2 stop bits

fXCK

fOSC

-----------

RxD / TxD

XCK

RxD / TxD

XCK

UCPOLn = 0

UCPOLn = 1

Sample

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