ATmega64A datasheet(177/392 Pages) ATMEL

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177

8160C–AVR–07/09

ATmega64A

xcko

Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

fosc

XTAL pin frequency (System Clock).

20.3.1

Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of

operation. The description in this section refers to Figure 20-2.

The USART Baud Rate Register n (UBRRn) and the down-counter connected to it function as a

programmable prescaler or baud rate generator. The down-counter, running at system clock

OSC), is loaded with the UBRRn value each time the counter has counted down to zero or when

the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This

clock is the baud rate generator clock output (= f

OSC/(UBRRn+1)). The transmitter divides the

baud rate generator clock output by 2, 8, or 16 depending on mode. The baud rate generator

output is used directly by the receiver’s clock and data recovery units. However, the recovery

units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the

UMSELn, U2Xn and DDR_XCK bits.

Table 20-1 contains equations for calculating the baud rate (in bits per second) and for calculat-

ing the UBRRn value for each mode of operation using an internally generated clock source.

Note:

1. The baud rate is defined to be the transfer rate in bit per second (bps).

BAUD

Baud rate (in bits per second, bps)

OSC

System Oscillator clock frequency

UBRR

Contents of the UBRRnH and UBRRnL Registers, (0 - 4095)

Some examples of UBRRn values for some system clock frequencies are found in Table 20-4 on

page 192 to Table 20-7 on page 195.

20.3.2

Double Speed Operation (U2Xn)

The transfer rate can be doubled by setting the U2Xn bit in UCSRnB. Setting this bit only has

effect for the asynchronous operation. Set this bit to zero when using synchronous operation.

Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling

the transfer rate for asynchronous communication. Note however that the Receiver will in this

case only use half the number of samples (reduced from 16 to 8) for data sampling and clock

recovery, and therefore a more accurate baud rate setting and system clock are required when

this mode is used. For the Transmitter, there are no downsides.

Table 20-1.

Equations for Calculating Baud Rate Register Setting

Operating Mode

Equation for Calculating

Baud Rate(1)

Equation for Calculating

UBRR Value

Asynchronous Normal

mode (U2Xn = 0)

Asynchronous Double

Speed mode (U2Xn = 1)

Synchronous Master

mode

BAUD

fOSC

UBRR 1n

()

------------------------------------------

UBRRn

fOSC

BAUD

------------------------

–

BAUD

fOSC

UBRRn 1

()

---------------------------------------

UBRRn

fOSC

BAUD

--------------------

–

BAUD

fOSC

UBRR 1n

()

---------------------------------------

UBRRn

fOSC

BAUD

--------------------

–

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