ATmega64A datasheet(155/392 Pages) ATMEL

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155

8160C–AVR–07/09

ATmega64A

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The

interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC2 pin. Setting the COM21:0 bits to two will produce a non-inverted PWM. An inverted PWM

output can be generated by setting the COM21:0 to three (see Table 17-5 on page 159). The

actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as

output. The PWM waveform is generated by clearing (or setting) the OC2 Register at the Com-

pare Match between OCR2 and TCNT2 when the counter increments, and setting (or clearing)

the OC2 Register at Compare Match between OCR2 and TCNT2 when the counter decrements.

The PWM frequency for the output when using phase correct PWM can be calculated by the fol-

lowing equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR2 Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the out-

put will be continuously low and if set equal to MAX the output will be continuously high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 17-7 OCn has a transition from high to low even though

there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-

TOM. There are two cases that give a transition without a Compare Match.

• OCR2 changes its value from MAX, like in Figure 17-7. When the OCR2 value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a higher value than the one in OCR2, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the

way up.

17.8

Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

T2) is therefore shown as a

clock enable signal in the following figures. The figures include information on when interrupt

flags are set. Figure 17-8 contains timing data for basic Timer/Counter operation. The figure

shows the count sequence close to the MAX value in all modes other than phase correct PWM

mode.

fOCnPCPWM

clk_I/O

N 510

⋅

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